Description
Model both single cycle and pipelined implementation of MIPS computer in Verilog that support a
subset of MIPS instruction set including:
• The memory-reference instructions load word (lw) and store word (sw)
• The arithmetic-logical instructions add, addi, sub, and, andi, or, and slt
• The jumping instructions branch equal (beq), branch not equal (bne), and jump (j)
Use Figure 1 as a top level block diagram of your single cycle implementation and Figure 2 for the
pipelined structure. Note: there may be some components and control signals omitted from the
figures that you will have to add to support all instructions listed above. Forwarding should be
implemented in the pipelined structure to handle data and control hazards. (source: Computer
Organization and Design, by Patterson and Hennessy, Morgan Kaufmann Publishers)
Figure 1. Single cycle implementation of MIPS architecture
Figure 2. Pipelined implementation of MIPS architecture
PROJECT REQUIREMENTS
This project must be modeled and simulated in Verilog HDL and synthesized by using Xilinx
synthesis tool. A simple MIPS assembly program using the supported instructions will be provided
to you to verify that the processor can execute those instructions continuously and correctly.
You must implement your pipelined processor in the Xilinx FPGA meeting the following
requirements:
• Error free in the simulation
• Be able to demonstrate on the FPGA board
• Demonstration results must coincide with your simulation results
• Demonstrate before the specified deadline.
TEAM ORGANIZATION
The Project 2 shall be team work. Each team is composed of 3 students, randomly grouped. The
work should be appropriately divided and distributed among all team members. Students are not
allowed to switch teams unless approved by the instructor.
DELIVERABLES
All deliverables should be submitted electronically on Canvas. The project must be demonstrated to
the TAs.
• Project report – The project report should be a written report including all the elaborated
aspects of the project. One submission is required for each team and should be submitted
electronically by one of the team members. Make sure names of all team members are clearly
shown on the cover page of the report.
• Peer Evaluation report – Each team member must also submit a peer evaluation report
describing your own contribution to the lab and to evaluate the performance of every
other team member, as explained below.
• Simulation result – In the final report, screen shots and explanations of simulation results must
be included. This will help you to earn partial credits if a project is not completed.
• RTL schematic – Generate the RTL schematic of your Verilog design by using Vivado. Include
the schematic in the project report.
• Source files – Include all your Verilog and any other source files in the report as appendix.
GRADING
• Working Verilog model (simulation): 40%
• Demonstrable and working FPGA implementation: 40%
• Project report: 20%
PEER EVALUATION
Each team member is required to provide a peer evaluation for your team for Project 2. The marks
of the peer evaluation should be integers ranging between 0 to 5, inclusively, with 5 indicating the
biggest contribution. A mark should be given to each team member including yourself according
the team member’s contribution based on your observation. A brief description of responsibilities of
each team member should also be provided, as shown in the following table.
Name
Level of
contribution
(0 ~ 5)
Responsibilities
(yourself)
(your lab partner)
(your lab partner)
Additionally, the teaching team (instructor and TAs) will give an oral examination to each team
member during the demonstration. We will ask some basic but important questions related to the
project. Basing on your answers, we will give an evaluation mark, ranging in between 0 to 5 as
well.
An average mark for individual contribution is calculated as:
Individual_Average = (sum of all team member’s marks + teaching team’s mark * 2) /
(number of team members + 2)
A group average is calculated as:
Group_Average = sum of all Individual_Average / number of team members
Then we calculate a difference ratio with the following equation:
Individual_Difference = Individual_Average / Group_Average – 1.0
Using the calculated Individual_Difference, we find a factor from the following lookup table.
Individual_Difference Factor Individual_Difference Factor
>=0 and < +10% 1.0 > -10% and < 0 1.0
>= +10% and < +20% 1.1 > -20% and <= -10% 0.9
>= +20% and < +30% 1.2 > -30% and <= -20% 0.8
>= +30% 1.3 <= -30% 0.7
Your final Project 2 grade is calculated as:
Final grade of Project 2 = overall points received * factor
The final grade of Project 2 will not exceed the maximum points assigned to the project. Following
table shows a sample.
Evaluator Member A Member B Member C
Member A 5 0 0
Member B 3 5 4
Member C 2 5 5
Teaching Team 3 5 4
Result Member A Member B Member C
Individual_Average (5+3+2+3*2)/5=3.2 (0+5+5+5*2)/5=4 (0+4+5+4*2)/5=3.4
Group_Average (3.2+4+3.4)/3=3.53
Difference 3.2/3.53-1=-9.3% 4/3.53-1=+13.3% 3.4/3.53-1=-3.7%
Factor 1.0 1.1 1.0
