Description
Cache Design
1 Set-associative Cache
Given a 2MB 4-way cache with 32-Byte cache lines; assume memory addresses are 32 bits, please answer the
following questions. (50 pts)
1. How many sets are there?
2. How many bits are needed for offset?
3. How many bits are needed for set index?
4. How many bits are there for the tag?
5. Given an memory address 0xBF F1F54D, which set does it map to? What are its tag and offset?
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2 Cache Replacement Policy
Consider the following set of an LRU cache,
LRU Q: E D C A
Way Data
0 A
1 C
2 D
3 E
Please answer the following questions. (30 pts)
1. If next request accessing data at address B, what do the set and the queue look like after this request?
2. If the 2nd request accessing data at address D, what do the set and the queue look like after this
request?
3. If the 3rd and 4th requests accessing data at addresses C and A, what do the set and the queue look
like after these two requests?
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3 Cache Performance
Please answer the following questions regarding average memory access time (AMAT). (20 pts)
1. If a specific cache design has 2% miss rate for a set of benchmarks with a hit latency of 20 cycles and
a miss penalty of 200 cycles. What is the AMAT for this cache?
2. If another cache design has 5% miss rate for the same set of benchmarks with a hit latency of 13 cycles
and a miss penalty of 200 cycles. What is the AMAT for this cache?
3. Which cache design is better?
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